G900 MemoryMap — различия между версиями

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*INCTRCADDR=0
 
*INCTRCADDR=0
 
|| DMA Command Address register for Channel 20
 
|| DMA Command Address register for Channel 20
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== Подключение ==
 
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{|border="1" cellpadding="5" cellspacing="0"
 
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! CHIP ||  Bus    || mmap I/O || Description
 
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|-
 
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| mDoc G4 || PXA SC0 ||  0x0000_0000 ||         
 
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|-
 
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| nand flash??? || PXA SC1 ||  0x0400_0000 ||         
 
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|-
 
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| [[Goforce 5500]] || PXA SC2 ||  0x0800_0000 ||  VLIO (32bit)       
 
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|-
 
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| ??? ||PXA SC4    ||  0x1000_0000 ||         
 
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|-
 
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| [[MSM6280]]      || PXA SC5 ||  0x1400_0000 || GSM Dual Port RAM (16bit)   
 
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|-
 
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| [[WM9714 ]] || PXA AC97 ||  ||  Sound
 
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|-
 
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| [[Marvell 88w8385]] || PXA SPI3 ||  ||  WIFI
 
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|-
 
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| ???              || PXA SPI2 ||  ||  Дактелоскопический сенсор
 
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|-
 
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| [[CSR 41814]]    || PXA BTUART ||  ||  Bluetooth
 
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|-
 
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| [[AK 4183]]      || PXA I2C ||  0x48 ||  Touchscreen
 
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|-
 
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| Qwerty KB      || PXA Matrix Keypad ||  || Клавиатура     
 
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|-
 
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| Buttons      || PXA GPIO ||  || кнопки     
 
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|-
 
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| Flashligth      || PXA GPIO ||  || вспышка     
 
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|-
 
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| bl kb и kp      || PXA GPIO ||  || подсветка клавиатуры и кнопок
 
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|-
 
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| [[G900_LCD]]      || [[Goforce 5500]] LCD || || Экран     
 
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|-
 
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| [[G900_LCD]] BL  || PXA PWM1 || || Подсветка экрана     
 
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|-
 
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| Camera 2mp      || [[Goforce 5500]] CAM ||  || камера сзади
 
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|-
 
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| Camera 0.3mp      || [[Goforce 5500]] CAM ||  || камера спереди   
 
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Версия 00:41, 24 декабря 2010

Memory Map

offset size mmap I/O Description
0x0000_0000 PXA SC0 0x0000_0000

DMA

WIN MOB Setting

Регистр Имя Значение Значение Description
0x4000_00E0 DRQSR0 0x00000000 DMA DREQ<0> Status register
0x4000_00E4 DRQSR1 0x00000000 DMA DREQ<1> Status register
0x4000_00E8 DRQSR2 0x00000000 DMA DREQ<2> Status register
0x4000_0130 DRCMR12 0x00000081 Request to Channel Map register for AC ’97 audio transmit request
0x4000_013C DRCMR15 0x00000089 Request to Channel Map register for SSP2 receive request
0x4000_0140 DRCMR16 0x00000088 Request to Channel Map register for SSP2 transmit request
0x4000_0154 DRCMR21 0x00000094 Request to Channel Map register for MMC/SDIO receive request
Channel 1
0x4000_0004 DCSR1 0x00000108
  • STOPINTR
  • REQPEND
 DMA Control/Status register for Channel 1
0x4000_0210 DDADR1 0xa0f53001
  • STOP
  • DADRR=0xA0F5300
 DMA Descriptor Address register for Channel 1
0x4000_0214 DSADR1 0xa0f54000
  • SRCADDR=0xa0f54000
 DMA Source Address register for Channel 1
0x4000_0218 DTADR1 0x40500040
  • TRGADDR=0x40500040
 DMA Target Address register for Channel 1
0x4000_021C DCMD1 0x9043c000
  • LEN=0x0
  • WIDTH=0b11 (Word 4 Bytes)
  • SIZE=0b11 (32 Bytes)
  • FLYBYT=0
  • FLYBYS=0
  • EndIrqEn=0
  • STARTIRQEN=1
  • ADDRMODE=0
  • CMPEN=0
  • FLOWTRG=1
  • FLOWSRC=0
  • INCTRGADDR=0
  • INCTRCADDR=1
 DMA Command Address register for Channel 1
Channel 8
0x4000_0020 DCSR8 0x40000008
  • STOPINTR
  • NODESCFETCH
 DMA Control/Status register for Channel 8
0x4000_0280 DDADR8 0x00000000 DMA Descriptor Address register for Channel 8
0x4000_0284 DSADR8 0xb2f62f0c DMA Source Address register for Channel 8
0x4000_0288 DTADR8 0x41700010 DMA Target Address register for Channel 8
0x4000_028C DCMD8 0x90014000
  • LEN=0x
  • WIDTH=1 byte
  • SIZE=8 Bytes
  • FLYBYT=0
  • FLYBYS=0
  • EndIrqEn=0
  • STARTIRQEN=0
  • ADDRMODE=0
  • CMPEN=0
  • FLOWTRG=1
  • FLOWSRC=0
  • INCTRGADDR=0
  • INCTRCADDR=1
 DMA Command Address register for Channel 8
Channel 9
0x4000_0024 DCSR9 0x40000008
  • STOPINTR
  • NODESCFETCH
 DMA Control/Status register for Channel 9
0x4000_0290 DDADR9 0x00000000 DMA Descriptor Address register for Channel 9
0x4000_0294 DSADR9 0x41700010 DMA Source Address register for Channel 9
0x4000_0298 DTADR9 0xb2eef70c DMA Target Address register for Channel 9
0x4000_029C DCMD9 0x60214000
  • LEN=0x0
  • WIDTH=1 byte
  • SIZE=8 Bytes
  • FLYBYT=0
  • FLYBYS=0
  • EndIrqEn=1
  • STARTIRQEN=0
  • ADDRMODE=0
  • CMPEN=0
  • FLOWTRG=0
  • FLOWSRC=1
  • INCTRGADDR=1
  • INCTRCADDR=0
 DMA Command Address register for Channel 9
Channel 20
0x4000_0050 DCSR20 0x40000008
  • STOPINTR
  • NODESCFETCH
 DMA Control/Status register for Channel 20
0x4000_0340 DDADR20 0x00000000 DMA Descriptor Address register for Channel 20
0x4000_0344 DSADR20 0x41100040 DMA Source Address register for Channel 20
0x4000_0348 DTADR20 0xa0f5d000 DMA Target Address register for Channel 20
0x4000_034C DCMD20 0x6003c000
  • LEN=0x0
  • WIDTH=4 Bytes
  • SIZE=32 Bytes
  • FLYBYT=0
  • FLYBYS=0
  • EndIrqEn=0
  • STARTIRQEN=0
  • ADDRMODE=0
  • CMPEN=0
  • FLOWTRG=0
  • FLOWSRC=1
  • INCTRGADDR=1
  • INCTRCADDR=0
 DMA Command Address register for Channel 20
Источник — «https://go900.angellfear.ru/index.php?title=G900_MemoryMap&oldid=435»